1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having an array voltage control circuit to maintain an array voltage supplied to a memory cell array at a predetermined level.
2. Brief Description of Related Art
An array voltage control circuit maintains constant a level of an array voltage by detecting it at the memory core region of a semiconductor memory device during predetermined operations including a bit line sensing and then supplying the electric charge relating to the amount of consumed electric charge through an external supply voltage.
FIG. 1 illustrates an array voltage control circuit. With reference to FIG. 1, the array voltage control circuit is constructed in a mesh power structure. The structure relates to a single memory cell array connected to a column decoder 20 and a row decoder 30. The control circuit includes a mesh power supply liner 10 for supplying the array voltage to required parts of the memory cell array through the mesh power structure. An array voltage feedback amplifier 40 compares the array voltage fed back through a feedback bus AVFBUS connected to the power supply liner 10 with the array reference voltage VREFA. The amplifier 40 amplifies the resultant difference. An array voltage driver 50 applies an array external supply power voltage to the mesh power supply liner 10 responsive to the array voltage feedback amplifier 40.
FIG. 2 illustrates an embodiment of paths through which the array voltage passes to memory cells in a core region of dynamic random access memory (DRAM). As shown in FIG. 2 sense amplifier includes a pull down N-type sense amplifier 5 and a pull up P-type sense amplifier 4 arranged in reference to an I/O gate 6. Memory cell arrays 2 and 3 are constructed with a plurality of memory cells (MCs) connected to crossing points between a word line WL and bit lines BL and BLB. When a sense amplifier driving signal (LAPG) is applied at a low logic level during a data access process, an array voltage VccA applied from the mesh power supply liner 10 is provided to a node NO1 through a P-type MOS transistor PM1. The array voltage VccA applied to the node NO1 is supplied to the sense amplifier 4.The sense amplifier 4 performs detection and amplification operations responsive to a potential difference in the pair of bitlines BL and BLB. The array voltage, therefore, is used as a power source for memory cell operations. Each memory cell is constructed with an access transistor AT and a storage capacitor SC. In the case of a 512 mega-bit DRAM, 4 banks exist, each consisting of 128 megabits. One bank is constructed with 768 subblocks. One subblock is constructed with 512xc3x97352 memory cells. The array voltage VccA is applied by one mesh unit covering one subblock.
The array voltage control circuit operates as follows. When electric charge stored at the mesh power supply liner 10 is consumed by cell operations, e.g., a bitline sensing operation, the array voltage is reduced. The reduced array voltage is applied to an inverter terminal (xe2x88x92) of the array voltage feedback amplifier 40 through a feedback bus AVFBUS. The array voltage feedback amplifier 40 compares the fed back array voltage applied to the inverter (xe2x88x92) terminal with an array reference voltage applied to an un-inverted terminal (+) and generates the amplified feedback output in proportion to a resultant difference. An array voltage driver 50 receives an output of the array voltage feedback amplifier 40. If the voltage driver 50 is constructed with P-type MOS transistors P1-P12 the driver 50 outputs a drive voltage reduced in proportion to the output of the amplifier 40. In other words, the array voltage driver 50 is constructed with P-type MOS transistors, the feedback output is proportionally reduced by as much as the array voltage has been reduced in comparison with the array reference voltage. The feedback output VINTAEB of the array voltage feedback amplifier 40 is commonly applied to gates of the P-type MOS transistors of the array voltage driver 50 through a feedback amplifier output bus FAOBUS. If the feedback output VINTAEB respectively controls the gates of the transistors, all array external supply voltage VDDA is simultaneously applied to the mesh power supply liner 10 through drains of the transistors . Accordingly, the reduced level of array voltage at the mesh power supply liner 10 increases again to the level of array reference voltage. The array voltage gets to the array reference voltage in the process of the array voltage control operations. The increase in the array voltage is transmitted to the array voltage feedback amplifier 40 through the feedback bus AVFBUS. At this time, the feedback output VINTAEB is increasingly controlled for respective applications to the gates of the P-type MOS transistors. As a result, the P-type MOS transistors P1-P12 are turned off to shut down further inflow of electric charge, thereby maintaining the level of array voltage relevant to the array reference voltage.
The array voltage control circuit thus constructed includes a mesh power supply liner 10 corresponding to one memory cell array connected to a single column decoder and a single row decoder and a feedback loop for applying an array external supply voltage to the mesh power supply liner 10. Thus, the feedback loop includes the array voltage feedback amplifier 40 connected with a single feedback bus AVFBUS.
As integration increases in a semiconductor memory device, so do the dimensions of a memory cell array region. Particularly, a square chip is preferred due to packaging convenience. In a square chip, the horizontal and vertical lengths of an integrated memory chip are identical.
The length of the output bus FAOBUS of the array voltage feedback amplifier 40 increases and the number of MOS transistors constructing the array voltage driver 50. These increases cause a significant increase in the height of the memory cell array region increasing the load to be taken by the output of the array voltage feedback amplifier 40. The result is a big difference between the array supply voltage and the array reference voltage and a deterioration in the voltage response characteristics. This deterioration, in turn, might render the feedback operations unstable where the supply and control operations of array supply voltage cannot be rapidly performed.
Put differently, if the feedback output turns on the MOS transistors in the driver 50 due to a large output load, it takes longer to sufficiently replenish the electric charge. Even if the feedback output turns into the MOS transistors of the array voltage driver 50, it may take long to do so.
And the array voltage control circuit might become unstable during memory cell access operations. This results in increased restoring time restoring operation of relevant data at the time of sensing the bitlines. As a result, the array voltage control circuit deteriorates high speed operations of semiconductor memory devices.
An abject of the present invention is provide a semiconductor memory device having an improved array voltage control circuit that addresses the disadvantages associated with prior circuits.
It is another object of the present invention to provide a control method and the related circuit that can stably supply an array voltage and provide a faster feedback response.
It is still another object of the present invention to provide a semiconductor memory device having an array voltage control circuit and a related array voltage control method that can stabilize memory cell access operations in an array and minimize restoration of stored data at the time of bitline sensing.
It is still another object of the present invention to provide an array voltage control circuit having a plurality of feedback loops in a semiconductor memory device.